The present invention relates to a technology effectively applicable to a data processor having a clock pulse generation circuit and particularly to a data processor which operates at low voltages and consumes relatively large power.
Patent document 1 describes the microcomputer's power-on reset technology in accordance with a power-on sequence. Patent document 2 describes the microcomputer's clock generation circuit having variable frequencies. There is considered a case of changing a frequency and an operating voltage. When the clock signal frequency and the operating voltage are increased, an attempt is made to prevent malfunction by avoiding an instance of increasing the frequency before increasing the operating voltage. Patent document 3 describes that the microprocessor and the peripheral circuit completely operate on the time-sharing basis in consideration for an increase in the power consumption when clocks are simultaneously supplied to the microprocessor and the peripheral circuit.
[Patent document 1]
    Japanese Unexamined Patent Publication No. Hei 5 (1993)-333963[Patent document 2]    Japanese Unexamined Patent Publication No. Hei 7 (1995)-287699[Patent document 3]    Japanese Unexamined Patent Publication No. Hei 9 (1997)-231195